Design and Evaluation of a 45 nm Charge Recovery Logic ALU for RISC-V Arithmetic Operations

Modern digital systems are increasingly constrained by power consumption, especially as embedded processors, wearable devices, IoT sensors, and battery-powered electronics continue to demand longer operating lifetimes. Conventional CMOS logic remains the dominant technology for digital computation, but its switching behavior dissipates energy as heat each time internal capacitances charge and discharge. As processor designs continue to scale, architectural techniques such as clock gating, voltage scaling, and pipeline optimization provide diminishing returns because they do not directly change the energy loss mechanism at the logic-gate level. This creates a need for alternative circuit design approaches that reduce power from the foundation of digital computation.

Charge Recovery Logic (CRL), also known as adiabatic logic, offers a promising path toward lower-energy digital circuits by recycling part of the charge that would normally be lost during switching. Instead of using a static supply voltage, CRL uses a time-varying power-clock that provides both energy and timing to the logic gates. Prior academic work has shown that CRL can reduce power consumption in benchmark circuits, but practical adoption remains limited because CRL requires custom circuit structures, differential signaling, careful phase synchronization, and a design flow that differs significantly from standard CMOS methods. These challenges become more significant when CRL is applied to larger processor-related blocks rather than isolated gates.

The objective of this project is to design and evaluate a 45 nm Charge Recovery Logic ALU for low-power RISC-V arithmetic operations. The system is built from custom transistor-level CRL components, including a CRL inverter/buffer, a 32-bit CRL full adder, and an ALU structure that supports a defined subset of RISC-V ALU instructions through mapped test vectors. The 32-bit full adder uses a latency4_custom8 architecture, dividing the datapath into four 8-bit custom adder groups to align arithmetic computation with the four-phase CRL power-clock model. The CRL inverter also functions as a buffer when its differential outputs are swapped, allowing signal restoration and improved phase-to-phase handoff.

By comparing the CRL arithmetic blocks against traditional CMOS references using functional correctness, average power, peak power, and energy per cycle, this project evaluates whether CRL can serve as a practical foundation for low-power processor datapaths. The work demonstrates a path toward applying charge recovery principles to RISC-V-compatible arithmetic hardware while identifying the timing, synchronization, and validation requirements needed for future CRL-based processor development.